Method and structure in the manufacture of mask read only memory

ABSTRACT

A method and structure of manufacture of mask ROM device is provided. Firstly, a semiconductor structure is provided that comprises a first dielectric layer, a plurality of buried bit lines and a plurality of code areas, wherein each of the code areas is placed between two buried bit lines. Next, a second dielectric layer having a plurality of contact plugs is formed on the semiconductor structure, wherein the contact plug comprises a second dielectric layer and a first glue layer, furthermore; the first glue layer is placed on the side-wall and bottom of the contact plugs. In addition, the contact plugs filled with the first metal layer. Then, a second glue layer, a second metal layer and a pad layer having an opening pattern are respectively formed on the second dielectric layer and contact plug. Thus, the processes of the present invention can improve the stability and accuracy in the electricity of the mask ROM device.

PRIORITY REFERENCE TO RELATED APPLICATION

This application is a divisional of, claims priority to, andincorporates by reference U.S. patent application Ser. No. 10/807,795filed Mar. 23, 2004 and entitled “Method and Structure in theManufacture of Mask Read Only Memory.”

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a method and structure in the manufacture ofsemiconductor memory devices, and more particularly to method andstructure of manufacture of mask ROM memory devices.

2. Description of the Prior Art

A memory device is widely used in the information industry, and isparticularly used in microprocessors and computers. In order to achievea faster speed of information exchange with a tremendous quantity, theinformation product needs the properties that are necessarily small insize and a reduced weight. Besides, the program and operation performedthe software has become complicated in the recent years so that theproperties are necessarily manufacturing a memory with a higher memorycapacity and faster access speed. Therefore, a mask ROM with highermemory capacity, higher integrity and faster access speed is currently acommon memory structure.

However, when the dimension of the mask ROM device goes below 0.35microns or smaller, a gap between 0 to 1 has become smaller in theelectricity because of the device margin and narrower line width. Hence,the demanded process window is also getting smaller. When the processwith the bigger dimension of the device is completely imitated to asmaller dimension, it could not get a preferred yield due to differentproperties and different structure with Inter-Layer Dielectric (ILD)between two products.

FIG. 1A to FIG. 1D is the method and structure of manufacture inconventional mask ROM memory devices 100. Referring to FIG. 1A,providing a semiconductor substrate 101 firstly, such as P type siliconsubstrate, wherein the semiconductor substrate 101 comprises a pluralityof buried N+ bit lines 103 therein. Next, a gate oxide layer 105 and aplurality of polysilicon word lines 107 are respectively formed on thesemiconductor substrate 101. Then, an inter layer dielectric 109, thematerial could be Borophosphosilicate Glass (BPSG), is formed on thepolysilicon word lines 107. After that, forming a glue layer 111 on theinter layer dielectric 109.

Following that, referring to FIG.1B, forming a photoresist layer 113 onthe glue layer 111, and performing a photolithography and etchingprocess to the photoresist layer 113 in order to form a first opening112 therein. The photoresist layer 113 having a first opening 112 isformed on the surface of the glue layer 111.

Subsequently, referring to FIG. 1C, utilizing the photoresist layer 113having a first opening 112 as a photomask and then performing a dryetching process in the glue layer 111. Therefore, the second opening 115are formed on the surface of the inter layer dielectric (ILD) 109 andwithin the glue layer 111. Next, removing the photoresist layer 113.Then, performing a step of ion implantation 117 in the mask ROM device100 so as to form the code areas 119 within the semiconductor substrate101.

Continue referring to FIG. 1C, as a result it has to etch the glue layer111 before forming the code areas 119 in the mask ROM device 100, thoughthe inter layer dielectric 109 which is an oxide layer below the gluelayer 111. Hence, etching the glue layer 111 will have a phenomenon ofover etching within the inter layer dielectric 109, which could notprecisely control the thickness of the inter layer dielectric 109 aftereach etching. Moreover, the etching process will also produce a profilewith bevels in the inter layer dielectric 109. For that reason; thephenomenon of over etching and the profile with bevels in the interlayer dielectric 109 will influence the implanted profile and implanteddepth of the code areas 119 in the semiconductor substrate 101 when ionimplanting in the mask ROM device 100. Also, the threshold voltage ofthe mask ROM device 100 is decided by the implanted ion concentration sothat the profile with bevels and the phenomenon of over etching willcause the implanted ion distribute non-uniformly. Therefore, it causesthe electricity unstably in the mask ROM device 100; moreover, the yieldwill also be influenced.

In addition, due to the fact that the etching process to the mask ROMdevice 100 is performed first, and then the implantation of ROM code,which decides the order-form from the users. However, the second opening115 is accessible to oxidize so as to form an oxide layer on the surfacewhile waiting for an order-form. (Because the bottom of the secondopening 115 is an inter layer dielectric 109) Therefore, after receivingthe order-form from users, it has to perform an etching or cleaningprocess to the second opening 115 so as to remove the oxide layer, whichis formed already. Then, performing the ion implantation following that,so the manufacturing time and manufacturing cost will be improved.

Still, after accomplishing the etching process to the glue layer 111,the second opening 115 produced therein has a negative bias with acritical dimension. Thus, in order to maintain the critical dimensionalafter the etch inspection as the same as the photomasks criticaldimensional after etching the glue layer 111 (it means to broaden thecode areas 119), the post exposure process of the photoresist layer 113has to be preformed when doing the photolithography process. However,the patterned photoresist layer and the non-patterned photoresist layerare exited simultaneously on the photoresist layer 113 (the patternedphotoresist layer with respects to the implant region, the non-patternedphotoresist layer with respects to the non-implant region). Therefore,the process window of the photoresist layer, which is above thenon-implant region will be influenced and reduced, even vanished duringthe post exposure process. This situation will make the device 10inaccurate with electricity.

Finally, referring to FIG. 1D, utilizing a sputtering method to form ablanket layer of metal 121, which uses as an electric connection withthe polysilicon word lines 107, on the mask ROM device 100 and down tothe code areas 119.

As mentioned above the process of the conventional mask ROM, theconventional mask ROM device has problems with inaccuracy andunstability in the electricity because etching the glue layer and postexposing to the photoresist layer. Hence, a method of manufacture ofmask ROM memory devices is required to overcome the problems of theprocess in the prior art.

SUMMARY OF THE INVENTION

It is an objective of the present invention to provide a method andstructure in the manufacture of a mask ROM(read only memory) device thatutilizes a step of blanket etching back to the first glue layer so thatthe phenomenon of over etching is not produced in the second dielectriclayer. It means that the profile of the implanted depth will not beinfluenced by over etching. Hence, the stability of the device will beenhanced and have a good yield.

It is another objective of the present invention to provide a method andstructure in the manufacture of a mask ROM device that directly definesthe critical dimension of the second opening on the photoresist layerthat the post exposing process is not necessary to perform. Therefore,the accuracy of the device is improved.

It is a further objective of the present invention to provide a methodand structure in the manufacture of a mask ROM device that deposits afirst metal layer on a first glue layer. However, the steps ofplanarizing the first metal layer and forming the code areas in the maskROM device wait until receiving the order-form from a user so that thesecond dielectric is not oxidized while waiting on an order-form. Hence,the manufacturing time and manufacturing cost will be reduced.

According to a preferred embodiment of the present invention, a methodand structure of manufacture of mask ROM device is provided. Firstly, asemiconductor structure comprises a first dielectric layer thereon, aplurality of buried bit lines and a plurality of code areas, whereineach of the plurality of code areas are placed between two of pluralityof the buried bit lines therein. Next, a second dielectric layer havinga plurality of contact plugs is formed on the semiconductor structure.Furthermore; the first glue layer is placed on the side-wall and bottomof the contact plug. In addition, the contact plug filled with the firstmetal layer. Then, a second glue layer, a second metal layer and a padlayer with an opening pattern are sequentially formed on the seconddielectric layer and contact plug.

BRIEF DESCRIPTION OF THE DRAWINGS

The objectives and features of the present inventions as well asadvantages thereof will become apparent from the following detaileddescription, considered in conjunction with the accompanying drawings.It is to be understood, however, that the drawings, which are not toscale, are designed for the purpose of illustration and not as adefinition of the limits of the invention, for which reference should bemade to the appended claims.

The present invention can be the best understood through the followingdescription and accompanying drawings, wherein:

FIG. 1A to 1D shows a schematically cross-sectional views of the varioussteps of a conventional method and structure in the manufacture of amask ROM process;

FIG. 2A to 2H shows a schematically cross-sectional view of the varioussteps of the present invention that a method and structure in themanufacture of a mask ROM according to a preferred embodiment of thepresent invention; and

FIG. 2I is a top view of a mask ROM device, schematically illustrating alayout according to a preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 2A to FIG. 2H shows the process flow in accordance with a preferredembodiment of this invention for producing a mask ROM device 200.Referring to FIG. 2A, a semiconductor structure is provided firstly. Thesemiconductor structure comprises a silicon substrate 201, such as a Ptype silicon substrate, a gate oxide layer 205 is on the siliconsubstrate 201, a polysilicon word lines 207 is on the gate oxide layer205, a first dielectric layer 209 is on the polysilicon word lines 207and a second dielectric layer 211 with a thickness about 3000-10000Å(angstroms), which is preferably about 5000 Å, on the first dielectriclayer 209. The second dielectric layer 211 is utilized as insulationbetween the semiconductor device structures, and the material could beBorophosphosilicate Glass (BPSG). Besides, the silicon substrate 201comprises a plurality of buried bit lines 203 therein, wherein thepolysilicon word lines 207 orthogonally oriented with respect to theburied bit lines 203. The polysilicon word lines 207 extendingtransversely from left to right across the mask ROM device 200.

Following that, referring to FIG. 2B, a photoresist layer (not shown inthe figure) having open pattern formed on a surface of the seconddielectric layer 211. Performing a photolithography and etching processto the photoresist layer in order to form the first opening 213 in thesecond dielectric layer 211, and exposing a portion of the surface ofthe first dielectric layer 209. Then, forming an interim blankettitanium layer on the second dielectric layer 211, a side-wall andbottom of the first opening 213. Next, performing a rapid thermalannealing (RTA) process to convert the interim titanium layer to thefirst glue layer 215, for instance titanium/titanium nitride thatutilizes to improve the adhesion with other metal layers, as shown inFIG. 2C.

Subsequently, as shown in FIG. 2D, a first metal layer 217 is depositedon the surface of the first glue layer 215, for instance blankettungsten that filled the first opening 213 and covered the surface ofthe first glue layer 215. Next, planarizing the first metal layer 217,for instance utilizing a method of chemical mechanical polishing or dryetching with conditions that have a higher ratio to tungsten and use thefirst glue layer 215 as an etch end point. Therefore, the surface of thefirst glue layer 215 and first opening 213, which is filled with thefirst metal layer 217, both are exposed. Then, a contact plug 216 isformed within the second dielectric layer 211, as shown in FIG. 2E.

Thereupon, referring to FIG. 2F, after planarizing the first metal layer217, utilizing a method of chemical mechanical polishing or dry etching,for instance plasma etching or reactive ion etching to perform a blanketetching back to the first glue layer 215, which is outside the contactplug 216. Hence, the surface of the second dielectric layer 211 isexposed. As a result, the blanket etching back process is executed tothe first glue layer 215, the first glue layer 215 and a portion of thesecond dielectric layer 211 below the first glue layer 215 will both beremoved. Therefore, the phenomenon of the over etching in the seconddielectric layer 211 can be avoided when the first glue layer 215 isremoved by dry etching.

Next, referring to FIG. 2G, a patterned photoresist layer 219 is formedboth on the surface of the second dielectric layer 211 and contact plug216. Etching the photoresist layer 219 in order to form the secondopening 211 within the photoresist layer 219 and expose a portion of thesecond dielectric layer 211. In accordance with the position of theplurality of the buried bit lines 203, the second opening 211 is placedbetween two of the plurality of buried bit lines 203 and far away fromthe contact plug 216. After that, utilizing the photoresist layer 219having the second opening 221 used as a mask to perform a ionimplantation process 223 in the mask ROM device 200. The boron ions areimplanted into the silicon substrate 201 through the second opening 221within the photoresist layer 219 in order to form a plurality of codeareas 224 in the silicon substrate 201, and between the two of theplurality of buried bit lines 203. The range of the implanted energy isabout 200-1000 keV, preferably is about 300 keV.

It is noted that the processes for encoding the ROM device with adesired code, such as an execution program code, are performed at themask ROM device 200. Users who order the ROM device 200, usuallydetermine the program code, thus the program code may be different fromeach other. The following steps of planarizaiton for the first metallayer 217 and formation of the code areas 224 in the mask ROM device 200can wait for an order-form from the users. Therefore, it can avoid thesecond dielectric layer 211 from becoming oxidized and form an oxidelayer thereon while waiting for an order-form from the users.Furthermore, the semiconductor structure does not need to clean orremove the oxide layer, therefore the manufacturing time andmanufacturing cost of the mask ROM device 200 are greatly reduced.

Due to the fact that one of the characteristic of the present inventionis blanket etching back to the first glue layer 215, and then performingthe step of defining the ROM code to the mask ROM device 200. Thus, thephenomenon of over etching will not happen in the second dielectriclayer 211, that is to say; the profile with the bevels in the seconddielectric layer 211 would not be occurred. Consequently, afterperforming the ion implantation process 223 in the mask ROM device 200,the code areas 224 in the silicon substrate 201 without the profile withbevels therein. For that reason, the boron ions can distribute uniformlyin the code areas 224, which can improve the stability of the mask ROMdevice 200, and enhance the yield.

Still, another characteristic of the present invention directly definesthe size of the second opening 221 on the photoresist layer 219 so thatthe critical dimension of second opening 221 is directly decided by theability of development with a stepper. It means that the photoresistlayer 219 would not be post exposed in order to broaden the code areas224 because of the critical dimension bias of the second opening 221which is negative. Accordingly, the photoresist layer, which is abovethe non-code areas will not be reduced, even vanished. Hence, it canmaintain the accuracy of the mask ROM device 200, and have a good yield.

As soon as the ion implantation 223 is performed in the mask ROM device200, referring to FIG.2H, the photoresist layer 219 is removed. Then, asecond glue layer 225, such as liner titanium/titanium nitride, with athickness of about 100-500 microns, preferably is about 350 microns isformed on the second dielectric layer 211 and contact plug 216. Theformation of the second glue layer 225, for instance utilizingsputtering, chemical vapor deposition or physical vapor deposition, thatdeposits a titanium layer on a surface of the second dielectric layer211 and contact plug 216. Next, the titanium layer is nitrogenized bynitrogen gas or ammonium gas at a high temperature environment so as toconvert the titanium layer into the titanium nitride layer on thesurface of the second dielectric layer 211 and the contact plug 216.Following that, a second metal layer 227, such as aluminum, is formed onthe surface of the second glue layer 225 that uses as transmission andconnection in electricity within the mask ROM device 200. After that, apad layer 229, such as silicon dioxide layer, is formed on the secondmetal layer 227 by chemical vapor deposition. Then, the third opening231 is formed within the pad layer 229 by using photolithographyprocess, wherein the third opening 231 is used as an electric connectionwith outside when packaging the mask ROM device 200. Finally, thepresent invention of the process for the mask ROM device is successivelyaccomplished.

FIG.2I shows a layout of mask ROM device 200 including the plurality ofburied bit lines 203 in the semiconductor substrate, polysilicon wordlines 207 orthogonally oriented with respect to the buried bit lines 203and overlying the buried bit lines 203. The second metal layer 227overlies on the buried bit lines 203, and the second metal layer227overlies on the polysilicon word lines 207. A mask ROM code areas 224with rectangle shape are placed between two buried bit lines 203.

The preferred embodiments are only used to illustrate the presentinvention, not intended to limit the scope thereof. Many modificationsof the preferred embodiments can be made without departing from thespirit of the present invention.

1. A structure of mask read only memory, comprising: a semiconductorstructure having a first dielectric layer thereon, a plurality of buriedbit lines and a plurality of code areas within said semiconductorstructure, wherein each of said plurality of code areas is placedbetween two of plurality of said buried bit lines; a second dielectriclayer having a contact plug being placed on said semiconductorstructure, wherein said contact plug comprises a first metal layertherein and a first glue layer thereon; a second glue layer being onsaid second dielectric layer and said contact plug; a second metal layerbeing on said second glue layer; and a pad layer being on said secondmetal layer.
 2. The structure of mask read only memory according toclaim 1, wherein said first dielectric layer is above said plurality ofburied bit lines.
 3. The structure of mask read only memory according toclaim 1, wherein said first metal layer is filled in said contact plug.4. The structure of mask read only memory according to claim 1, whereinthe material of said first metal layer is tungsten.
 5. The structure ofmask read only memory according to claim 1, wherein the material of saidsecond dielectric layer is Borophosphosilicate Glass (BPSG).
 6. Thestructure of mask read only memory according to claim 1, wherein thematerial of said first glue layer is titanium/titanium nitride (Ti/TiN).7. The structure of mask read only memory according to claim 1, whereinsaid second glue layer comprises linear titanium/titanium nitride(Ti/TiN).